1. Field of the Invention
The present invention relates to a semiconductor device typically to be used for a switching device that is structurally featured to stably control the lifetime of carriers, and a method of manufacturing the same.
2. Discussion of the Background
The technique of controlling the lifetime of carriers is important for semiconductor devices used for switching devices such as thyristors to realize a swift switching action, because carriers can be annihilated quickly for a swift switching action when the switch is turned off by shortening the carrier lifetime.
With a known and commercially popular technique of shortening the carrier lifetime, a semiconductor substrate is irradiated typically with protons to produce a defect layer in the semiconductor substrate and utilize the defect layer as recombination centers for carriers.
Particularly, it is well known that in the case where a defect layer is formed in the vincity of the junction plane between a p-type semiconductor layer and an n-type semiconductor layer, it is possible to efficiently annihilate the carriers because the holes as minor carriers injected into the n-type semiconductor from the p-type semiconductor can be swiftly recombined with the electrons when the reverse bias is applied.
FIG. 1 of the accompanying drawing illustrates a conventional semiconductor device, which is a diode in which a defect layer is formed. The illustrated known diode comprises an n-type semiconductor substrate 1, a p-type semiconductor layer 4 formed in part of the n-type semiconductor substrate 1 to realize a pn junction on the interface of the p-type semiconductor layer 4 and the n-type semiconductor substrate 1. The p-type semiconductor layer 4 and the n-type semiconductor substrate 1 are connected to electrodes 3 and 6, respectively. The diode further comprises a defect layer 5 in the n-type semiconductor substrate 1 of the pn junction.
In such a semiconductor device, a defect layer 5 can be produced by irradiating a device that has been prepared by forming a p-type semiconductor layer 4 in part of an n-type semiconductor substrate 1 and then forming electrodes 3 and 6 thereto, with protons typically at a dose of 1 to 5,000.times.10.sup.10 cm.sup.-2 and accelerating them with an energy level of 0.5 to 4.0 MeV.
With the consideration of a width of the formed defect layer 5, the acceleration energy is selected so that each position where the protons are stopped has a little depth from the pn junction plane and the defect layer 5 contacts with the pn junction plane. For example, the position where the protons are stopped may be selected to be 5 .mu.m further deeper than that of the pn junction plane because the HWHM of the defect layer is generally assumed to be approximately 5 .mu.m.
However, it is difficult to control to form the defect layer 5 so as to always contact with the pn junction plane. If the defect layer 5 overlaps the p-type semiconductor layer 4, the region of defect layer overlapping the p-type semiconductor layer 4 does not contribute to the shortening of lifetime, resulting in lowered switching performance. Also, the degree of lowering of the switching performance is dispersed because the volume of the overlapping region is changed.
Since such a defect layer is easily recovered at the temperature of 300 to 400.degree. C. and does not result in the recombination center for carriers, a thermal process can be generally carried out after the irradiation with protons. For forming Al electrode 3, for example, the thermal process referred to as a sintering whose temperature is approximately 400.degree. C. is required. Accordingly, the irradiation with protons is generally executed in the last step of the semiconductor manufacturing.
In order to swiftly annihilate carriers injected into the n-type semiconductor layer 1 from the p-type semiconductor layer, it is preferable to form the defect layer 5 in the vicinity of the pn junction plane. By the irradiation with protons from the reverse side of the semiconductor substrate, it is possible to prevent the defect layer from overlapping the p-type semiconductor layer 4. However, since the semiconductor substrate has the width of several hundred micrometers and it requires very high acceleration energy to accurately form the defect layer in the vicinity of the pn junction plane, it is impossible to realize the above formation of the defect layers.
Moreover, the density of defect shows its maximum at the position where the protons are stopped, in which a small number of defects are produced. Assume that, in this condition, the irradiation with protons is executed from the reverse side of the semiconductor substrate 1. Consequently, the defects are produced in the n-type semiconductor layer 1, resulting in increase of the resistance of the n-type semiconductor layer 1.
Due to these reasons, the irradiation with protons is executed from the reverse side of the semiconductor substrate after the formation of the interlayer insulation film 2, the Al electrode 3, or the like. Thus, there is a probability that the position where the protons are stopped is changed in accordance with the shape of the interlayer insulation film 2 or the Al electrode 3.
Moreover, there is a probability that the depth of the pn junction plane is changed in accordance with the dispersion of the impurity diffusion (e.g., boron) as the impurity constituting the p-type semiconductor layer 4, resulting in occurrence of the dispersion in the relative distance from the pn junction plane to the defect layer.
As described above, in the conventional semiconductor device and the method of manufacturing the same, the relative distance from the pn junction plane to the defect layer 5 is dispersed even when the depth of the emitted protons is uniform, with the result that the structure shown in FIGS. 2A and 2B is produced and its switching performance is dispersed.
FIG. 2A shows the case where the defect layer 5 overlaps the p-type semiconductor layer 4. With this structure, the region of the defect layer 5' overlapping the p-type semiconductor layer 4 does not contribute to the shortening of lifetime, resulting in lowered switching performance. Also, the degree of lowering of the switching performance is dispersed because the volume of the overlapping region 5' is changed.
FIG. 2B shows the case where the defect layer 5 is considerably apart from the pn junction plane. With this structure, particularly, in the case where a distance d from the defect layer 5 to the pn junction plane is larger than that of a carrier diffusion, the lifetime of the carrier injected from the p-type semiconductor layer 4 cannot be shortened by the defect layer 5, resulting in lowered switching performance.
FIG. 6 shows the relationship between on-voltage and switching speed in the semiconductor device. The semiconductor shows its superior performance at a higher switching speed and at a lowered on-voltage. Regarding a conventional semiconductor device, however, the switching speed is dispersed with respect to on-voltage.
Meanwhile, in the semiconductor devices as shown in FIG. 3, a defect layer 5 is formed to cover the entire transversal area of the n-type semiconductor substrate 1. Thus, all the electric current flowing from the electrode 3 to the electrode 6 pass through the defect layer 5 when the semiconductor device is on. The carriers passing through the defect layer 5 can be captured by the recombination centers and easily annihilated. The mobility of carriers is reduced in the defect layer 5 as they become scattered by the defects there. Due to these reasons, the defect layer 5 becomes a high resistance region in the semiconductor substrate 1 to give rise to a problem of raising the on-voltage of the semiconductor device.